1. Field of the Invention
The present invention relates to a system control device which controls a system LSI having a plurality of functional blocks integrated on a single chip.
2. Description of the Related Art
System control devices generally comprise a system control microcomputer section and a system LSI section which has a plurality of functional blocks integrated on a single chip. Each functional block comprises a control register. Portions of an address space which can be accessed by the system control microcomputer section are assigned to these control registers. The system control microcomputer section controls the system LSI section having the functional blocks by accessing the control registers. For example, a system control device which accesses a plurality of control registers is disclosed in Japanese Unexamined Patent Application Publication No. 2005-327078.
FIG. 9 is a block diagram showing a whole configuration of a conventional system control device and a schematic diagram showing an operation of the system control device.
In FIG. 9, the system control device 900 comprises a system control microcomputer section 910, an address decoding section 911, and a system LSI section 920 which has four Direct Memory Access (DMA) controllers 921, 922, 923 and 924 which are integrated on a single chip. The four DMA controllers 921 to 924 are controlled by control registers 925, 926, 927 and 928 which are provided therein. The control registers 925 to 928 are accessed and controlled by the system control microcomputer section 910. For the access, the address decoding section 911 decodes an access address to a control register which the system control microcomputer section 910 attempts to access, into an address assigned to the control register.
Here, the system control device 900 uses the four DMA controllers 921 to 924 to transfer four pieces of image data PA, PB, PC and PD stored in different address areas 931, 932, 933 and 934 of a main memory 930 to four buffer areas 941, 942, 943 and 944 of a buffer 940. The image data PA to PD transferred to the buffer 940 are combined by an image combining block 950 to generate combined image data ABCD.
The image data PA to PD stored in the address areas 931 to 934 of the main memory 930 are updated by access from the outside of the system control device 900 a predetermined period of time after being transferred to the buffer 940 by the DMA controllers 921 to 924. After being updated, the updated image data PA to PD are transferred again to the buffer areas 941 to 944 of the buffer 940, respectively, using the DMA controllers 921 to 924. The image data PA to PD transferred to the buffer 940 are combined into combined image data ABCD.
Regarding hardware design for system control devices, when a plurality of DMA controllers having the same function are mounted on hardware, it is often that DMA controllers having the same design data are mounted in parallel, so that the control registers of the DMA controllers have a common address or bit position in the DMA controllers. Specifically, when an address of 1000 of the DMA controller 921 is assigned to the address of the control register 925 in the DMA controller 921, addresses of 1000 of the DMA controllers 922 to 924 are also assigned to the addresses of the control registers 926 to 928 in the DMA controllers 922 to 924, respectively.
FIG. 10 is a schematic diagram showing access to the control registers 925 to 928 in the conventional system control device 900.
In FIG. 10, the control registers 925 to 928 are provided in the DMA controllers 921 to 924, respectively. The control registers 925 to 928 each have 32 bits (four bytes). The Least Significant Bytes (LSBs) of the control registers 925 to 928 include startup bits which are used to start up the respective DMA controllers 921 to 924.
The system control microcomputer section 910 is a 32-bit microcomputer. A register access bus (host bus) via which the control registers 925 to 928 are accessed has a width of 32 bits.
In the system control device 900, when the image data PA is transferred to the buffer area 941 in the buffer 940, the system control microcomputer section 910 accesses the LSB of the control register 925. In this case, the address decoding section 911 receives an access address to the LSB of the control register 925 from the system control microcomputer section 910, and issues an access control signal for the whole control register 925. In other words, when the LSB of the control register 925 is accessed, the access control signal is issued for the whole 32-bit control register 925.
When the system control device 900 is used to transfer the four pieces of image data PA to PD from the main memory 930 to the buffer 940, four access control signals are sequentially issued to the respective control registers 925 to 928 to access the LSBs of the control registers 925 to 928, thereby starting up the DMA controllers 921 to 924, which in turn perform the transfer.